This invention relates to a circuit arrangement for balancing a two wire, full duplex data transmission system, in which a transmitter and a receiver in one station are connected by two lines to a further transmitter and a further receiver in another station. The transmitters emit data signals which are transmitted through the lines to the receiver in the other station, and the transmitters are connected by a dummy circuit to their own receivers.
With a known two wire full duplex data transmission system, data are transmitted via two lines from a first station to a second station and vice versa. Each of the stations possesses a transmitter and a receiver and a plurality of impedances arranged in the form of a bridge circuit. A first and a second resistor of equal magnitude form a first and a second bridge impedance. A third bridge impedance is formed by the lines and by the components of the other station which are connected to the lines. A fourth bridge impedance is in the form of a balancing resistor and must be balanced in such manner that it is equal to the third bridge impedance. The transmitter is connected to the connection point of the first and the second bridge impedance and to the connection point of the third and the fourth bridge impedance into the bridge diagonal. The receiver is connected to the two remaining diagonal points.
In particular in the case of d.c. keying with a low transmitting level, simultaneous transmission of data in both directions is only possible, when, using the balancing impedances, the line is simulated as accurately as possible, so that during the operation of the transmitter its own receiver is not disturbed.
Prior art balancing impedances are formed from a plurality of parallel-connected time constant elements having adjustable capacitors and resistors. In the event of a change in the capacitance of one of the capacitors and in the event of a change in the resistances, not only is the time constant of the relevant time constant element altered, but also the amplitude characteristic of the balancing resistor. The mutual influence of the capacitors and resistors which are to be adjusted means that the desired balancing process is time-consuming and necessitates a long iterative procedure. Thus, this process has the disadvantage that it can only be carried out by trained personnel. The variable capacitances are generally realized with solid capacitors in combination with step switches, which necessitates a relatively large expense.
An object of the invention is to provide a circuit arrangement for balancing a two wire, full duplex data transmission system, which may be balanced more rapidly, more accurately, and with a lower cost than has been possible with prior art apparatus.